The invention relates to the field of making MOS or CMOS and bipolar devices on the same integrated circuit die, and, more particularly, to a single poly process utilizing polysilicon contacts to the transistors to minimize device size and silicide to reduce contact resistance.
It has long been known that it is desirable to be able to make CMOS or MOS and bipolar integrated devices on one integrated circuit die. Further, it has long been known that smaller cell sizes reduces the sizes of various parasitic and intrinsic capacitances which are present in all integrated circuits.
In the prior art, various processes to make MOS or CMOS and bipolar devices on the same integrated circuit existed. However, these processes were able to make only high performance bipolar devices or high performance MOS or CMOS devices, but not both. High performances CMOS devices use small amount of power and are small in area and have high yield whereas high performance bipolar devices have very fast switching times and are very small in area and have high yield. High performance MOS devices are small in size and have fast switching times relative to other prior MOS devices and have high yield.
One of the major barriers to accomplishing a process that would yield both high performance CMOS and high performance bipolar devices on the same die has been the increase in cell size and device size made necessary in order to make electrical contact by way of aluminum conductors to nodes in the cell or terminals of the device. It is always necessary in integrated designs to allow clearances for variations from intended feature sizes caused by manufacturing variations in the mask actually generated from that which was specified. Further, because of mask alignment errors in lining up a mask defining one feature that is supposed to fall within the perimeter of another feature, there must be a certain design rule clearance observed around the perimeter of the inner feature as measured to the perimeter of the outer feature. This means, for example, that is a minimum feature size contact hole for a source or drain contact is to be placed within the confines of a source or drain region adjacent a gate region in a MOS device, then the source or drain region must be made at least as being as the contact hole plus the minimum required clearance around the contact hole. This results in a bigger source or drain region than would be necessary if no contact hole for a metal contact line were used and, therefore, a bigger device results.
Further, if metal lines are used to interconnect the various device terminals and circuit nodes in a cell, the cell size will be larger for the same reasons previously outlined because of the necessity of forming a contact hole at every node to be connected to a metal line.
Still further, metal interconnect technology which causes changing levels in the topography of a circuit tends to render a particular technology non-scalable. A particular technology is scalable, if it is planar. That is, if photolithography is carried out on planar surfaces, then no depth of field problem causes distortion of feature sizes. Since, however, metal line contact holes must go all the way down through various preexisting layers to the surface of the silicon, deep holes and severe changes of levels in the topography result. These deep holes cause many problems having to do with metal step coverage and depressions in the surface of the device rendering it non-planar. Trying to do photolithography on a non-planar surface, causes the features sizes which are defined on the surface by the projected light to be distorted from the dimensions desired as defined on the masks through which the light was projected because of loss of clarity at the edges of the image, i.e., the image is in focus at only one distance from the lense. If the "screen" upon which the image is projected is not flat, the image will be out of focus in some areas. This leads to improper resist development. This makes it necessary to use larger clearances in the design rules to prevent the distorted shapes from causing defects. Consequently, the above problem adversely affects device density and renders scaling of the technology down in size by using smaller feature sizes and tighter design rules difficult or impossible.